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Preliminary
...the analog plus company TM
FEATURES D Provides Reference Clock And Synthesized Clock D 5 to 32 MHz Input Reference Frequency D Pin-to-Pin Compatible to Avasem AV9107 D Programmable Analog Phase Locked Loop
ST49C107A-04
Preprogrammed CPU Mother Board Frequency Generator
June 1997-3
D Low Power Single 5V CMOS Technology D Up to 16 Frequencies Stored Internally D 8/14 pin DIP or SOIC Package
GENERAL DESCRIPTION The ST49C107A-04 is a mask programmable monolithic analog CMOS device designed to generate two simultaneous clocks. The output frequency can vary from 2 to 130MHz, with up to 16 single selectable preprogrammed frequencies stored in internal ROM. The ST49C107A-04 is designed to replace existing CPU mother board clocks generated from individual oscillators ORDERING INFORMATION
Part No. ST49C107ACF14-04 Package 14 Lead 150 Mil JEDEC SOIC Operating Temperature Range 0C to 70C
in order to reduce board space and number of oscillators. To provide high speed and low jitter clock, the parts utilize a high speed analog CMOS phase locked loop using 14.318 MHz system clock as the reference clock (note that reference clock can be changed to generate optional frequencies from a standard programmed device). The programmed clock outputs are selectable via four address lines.
BLOCK DIAGRAM
XTAL XTAL OE1 OE2
Oscillator Circuit
Output Buffer
1X-CLOCK 2X-CLOCK
Programmable Counter B
Phase Detector
Charge Pump
Loop Filter
Voltage Controlled Oscillator
Programmable Counter C
Programmable Counter A
Voltage Reference Circuit
Rom Table Select Logic
B=5....128 A=5....128 C = 1, 2, 4
A0-A3
Figure 1. Block Diagram
Rev. P2.00
E1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
ST49C107A-04
PIN CONFIGURATION
Preliminary
A1 A2 A3 AGND DGND PD* XTAL1
1 2 3 4 5 6 7
14 13 12 11 10 9 8
A0 1XCLK VCC 2XCLK OE2 OE1 XTAL2
14 Lead SOIC (Jedec, 0.150")
PIN DESCRIPTION
Symbol A1 A2 A3 AGND DGND PD XTAL1 Pin # 1 2 3 4 5 6 7 Type I I I O O I I Frequency Select Address Input 21 . Frequency Select Address Input 31. Frequency Select Address Input 41. Analog Ground. Digital Ground. Power-down (Active Low). Shuts off chip when low1. Crystal Or External Clock Input. A crystal can be connected to this pin and XTAL2 pin to generate internal phase locked loop reference clock. For external 14.318 MHz clock, XTAL2 is left open or used as buffered clock output. Crystal Output. 1X-CLOCK Output Enable (Active High). 1X-CLOCK output is three stated when this pin is low1. 2X-CLOCK Output Enable (Active High). 2X-CLOCK output is three stated when this pin is low1. Programmed Output Clock. Positive Supply Voltage. Single +5 volts. 2X-CLOCK Divide-by-two Output. Frequency Select Address Input 11. Description
XTAL2 OE1 OE2 2XCLK VCC 1XCLK A0
8 9 10 11 12 13 14
O I I O I O I
Notes 1Have internal pull-up resistors on inputs.
Rev. P2.00 2
Preliminary
DC ELECTRICAL CHARACTERISTICS
ST49C107A-04
Test Conditions: TA = 0C to +70C, VCC = 5.0V 10% Unless Otherwise Specified
Symbol VIL VIH VOL VOH IIL IIH ICC ISB RIN Parameter Input Low Level Input High Level Output Low Level Output High Level Input Low Current Input High Current Operating Current Standby Current Input Pull-up Resistance 500 45 25 900 1300 2.4 -10 1 55 2.0 0.4 Min. Typ. Max. 0.8 Unit V V V V A A mA A k IOL = 8.0mA IOH = 8.0mA Except Crystal Input VIN=VCC No Load. CLOCK=100MHz No Load Conditions
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 0C to +70C, VCC = 5.0V 10% Unless Otherwise Specified
Symbol T1 T2 T4 T5 T3 T3 T T7 T8 Parameter 1X, 2X-CLOCK Rise Time 1X, 2X-CLOCK Fall Time Duty Cycle Duty Cycle Jitter 1 Sigma Jitter Absolute Input Frequency Buffered Clock Rise Time Buffered Clock Fall Time 2 40 45 Min. Typ. 1 1 50 50 0.5 3 Max. 2 2 60 55 2 5 32 20 20 Unit ns ns % % % % MHz ns ns Conditions CL=20pF 0.8V - 2.0V CL=20pF 2.0V - 0.8V 1.4V Switch Point VCC/2 Switch Point
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Volts Voltage at Any Pin . . . . . . . . . GND-0.3V to VCC +0.3V
Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . -40C to +150C Package Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW
Rev. P2.00 3
ST49C107A-04
EXTERNAL CLOCK CONNECTION
Preliminary
CLOCK OUTPUT TABLE FOR ST49C107A-04 (using 14.318 MHz input. All frequencies in MHz).
A3 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Factor 95/17 107/23 35/10 95/34 56/8 107/46 38/17 35/20 76/17 2 3 8 1/2 1/4 109/13 118/13 2XCLOCK 80.02 66.62 50.11 40.01 100.23 33.31 32.01 25.06 64.02 2X-Input 3X-Input 8X-Input 0.5X-Input 0.25XInput 120.00 129.96 CLOCK 40.01 33.31 25.06 20.00 50.11 16.66 16.00 12.47 32.01 1X-Input 1.5X-Input 4X-Input 0.25X-Input 0.125XInput 60.00 64.98
To minimize the noise pickup, it is recommended to connect 0.047 (F capacitor to XTAL1, and keep the lead length of the capacitor to XTAL1 to a minimum to reduce noise susceptibility.
FREQUENCY SELECT CALCULATION The ST49C107A-04 contains an analog phase locked loop circuit with digital closed loop dividers and a final output multiplexer to achieve the desired dividing ratios for the clock output. The accuracy of the frequencies produced by the ST49C107A-04 depends on the input frequency and divider ratios. The formula for calculating the exact output frequency is as follows: CLKOUT = CLKIN * Factor For proper output frequency, the ST49C107A-04 can accept a reference frequency from 5 - 32MHz with max output frequency of 130MHz (2X - clock).
0 0 0 0 0 1 1 1 1 1 1 1 1
1X-CLOCK 2X-CLOCK CLOCK T5
T1
T4
T2
T3
BCLK T8 T7
Figure 2. Timing Diagram
Rev. P2.00 4
Preliminary
ST49C107A-04
14 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC)
Rev. 1.00
D
14
8
E
1 7
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.337 0.150 MAX 0.069 0.010 0.020 0.010 0.344 0.157
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00
0.050 BSC 0.228 0.016 0.244 0.050
1.27 BSC 5.80 0.40 6.20 1.27 8
0 8 0 Note: The control dimension is the millimeter column
Rev. P2.00 5
ST49C107A-04
Preliminary
Notes
Rev. P2.00 6
Preliminary
ST49C107A-04
Notes
Rev. P2.00 7
ST49C107A-04
Preliminary
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P2.00 8

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